View EM68916DVAA-6H_4655654.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EtronTech
Etron Confidential
EM68916DVAA
Advanced (Rev. 1.0 Apr. /2009) Table 1. Ordering Information
Part Number EM68916DVAA-6H EM68916DVAA-75H Clock Frequency 166MHz 133MHz Data Rate IDD6 Package
8M x 16 Mobile DDR Synchronous DRAM (SDRAM)
Features
Fast clock rate: 166/133 MHz Differential Clock CK & CK Bi-directional DQS Four internal banks, 2M x 16-bit for each bank Edge-aligned with read data, centered in write data Programmable Mode and Extended Mode Registers * - CAS Latency: 2, or 3 - Burst length: 2, 4, or 8 - Burst Type: Sequential & Interleaved - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) * Individual byte writes mask control * DM Write Latency = 0 * Precharge Standby Current = 100 A * Self Refresh Current = 200 A * Deep power-down Current = 10 A max. at 85 * Auto Refresh and Self Refresh * 4096 refresh cycles / 64ms * No DLL (Delay Lock Loop), to reduce power; CK to DQS is not synchronized. * Power supplies: VDD & VDDQ = +1.8V+0.15V/-0.1V * Interface: LVCMOS * Ambient Temperature TA = -25 ~ 85 , * 60-ball 8mm x 10mm VFBGA package - Pb free and Halogen free * * * * *
333Mbps/pin 200 A VFBGA 266Mbps/pin 200 A VFBGA
VA: indicates VFBGA package A: indicates Generation Code H: indicates Pb and Halogen Free for VFBGA Package
Figure 1. Ball Assignment (Top View)
1 A B C D E F G H J K
VSS
2
DQ15
3
VSSQ
7
VDDQ
8
DQ0
9
VDD
VDDQ
DQ13
DQ14
DQ1
DQ2
VSSQ
VSSQ
DQ11
DQ12
DQ3
DQ4
VDDQ
VDDQ
DQ9
DQ10
DQ5
DQ6
VSSQ
VSSQ
UDQS
DQ8
DQ7
LDQS
VDDQ
VSS
UDM
NC
NC
LDM
VDD
CKE
CK
CK
WE
CAS
RAS
A9
A11
NC
CS
BA0
BA1
A6
A7
A8
A10/AP
A0
A1
VSS
A4
A5
A2
A3
VDD
Overview
The EM68916D is 134,217,728 bits of double data rate synchronous DRAM organized as 4 banks of 2,097,152 words by 16 bits. The synchronous operation with Data Strobe allows extremely high performance. EM68916D is applied to reduce leakage and refresh currents while achieving very high speed. I/O transactions are possible on both edges of the clock. The ranges of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.
EtronTech
Figure 2. Block Diagram
CK CK CKE
SELF REFRESH LOGIC & TIMER COMMAND DECODER CONTROL SIGNAL GENERATOR
EM68916DVAA
PASR, DS
CLOCK BUFFER EXTENDED MODE REGISTER
CS RAS CAS WE
Row Decoder Row Decoder Row Decoder Row Decoder
2M x 16 CELL ARRAY (BANK #0) Column Decoder
A10/AP
COLUMN COUNTER
MODE REGISTER
2M x 16 CELL ARRAY (BANK #1) Column Decoder
A0 A9 A11 BA0 BA1 LDQS UDQS DQ0 DQ15 ~ ~
ADDRESS BUFFER 2M x 16 CELL ARRAY (BANK #2) Column Decoder
REFRESH COUNTER
DATA STROBE BUFFER
DQ Buffer 2M x 16 CELL ARRAY (BANK #3) Column Decoder
LDM UDM
Etron Confidential
2
Rev. 1.0
Apr. 2009
EtronTech
Pin Descriptions
Table 2. Pin Details of EM68916D
Symbol CK, CK Type Input Description
EM68916DVAA
Differential Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK . Input and output data is referenced to the crossing of CK and CK (both directions of the crossing) Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self Refresh operation (all banks idle) or Active Power Down (Row Active in any bank). CKE is synchronous for all functions except for disabling outputs, which is asynchronous. Input buffers, excluding CK, CK and CKE, are disabled during Power Down and Self Refresh modes to reduce standby power consumption. Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. BA0 and BA1 also determine which mode register (MRS or EMRS) is loaded during a Mode Register Set command. Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge). Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and WE signals and is latched at the positive edges of CK. When RAS and CS are asserted "LOW" and CAS is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE signal. When the WE is asserted "HIGH," the BankActivate command is selected and the bank designated by BA is turned on to the active state. When the WE is asserted "LOW," the Precharge command is selected and the bank designated by BA is switched to the idle state after the precharge operation. Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS and WE signals and is latched at the positive edges of CK. When RAS is held "HIGH" and CS is asserted "LOW," the column access is started by asserting CAS "LOW." Then, the Read or Write command is selected by asserting WE "HIGH " or LOW"."
CKE
Input
BA0, BA1
Input
A0-A11
Input
CS
Input
RAS
Input
CAS
Input
WE
Input
Write Enable: The WE signal defines the operation commands in conjunction with the RAS and CAS signals and is latched at the positive edges of CK. The WE input is used to select the BankActivate or Precharge command and Read or Write command. Bidirectional Data Strobe: DQS is an output with read data and an input with write data. DQS is edge-aligned with read data, centered in write data. It is used to capture data. For x16, LDQS is DQS for DQ0-DQ7 and UDQS is DQS for DQ8DQ15.
LDQS, UDQS
Input / Output
Etron Confidential
3
Rev. 1.0
Apr. 2009
EtronTech
LDM, UDM Input
EM68916DVAA
Data Input Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled High along with input data during a Write access. DM is sampled on both edges of DQS. DM pins include dummy parasitic loading internally to match the DQ and DQS loading. For x16, LDM is DM for DQ0-DQ7 and UDM is DM for DQ8-DQ15. Data I/O: The DQ0-DQ15 input and output data are synchronized with the positive edges of CK and CK . The I/Os are byte-maskable during Writes. Power Supply: +1.8V+0.15V/-0.1V Ground DQ Power: +1.8V+0.15V/-0.1V. Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. No Connect: No internal connection, these pins suggest to be left unconnected.
DQ0 - DQ15 VDD VSS VDDQ VSSQ NC
Input / Output Supply Supply Supply Supply -
Etron Confidential
4
Rev. 1.0
Apr. 2009
EtronTech
Operation Mode
EM68916DVAA
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 3 shows the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set Extended Mode Register Set No-Operation Device Deselect Burst Stop AutoRefresh SelfRefresh Entry SelfRefresh Exit Power Down Mode Entry Power Down Mode Exit Deep Power Down Entry State Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Idle Idle Any Any Active(4) Idle Idle Idle (Self Refresh) Idle/Active(5
)
CKEn-1 CKEn DM BA1 BA0 A10 H H H H H H H H H H H H H H L H L H X X X X X X X X X X X X H L H L H L X X X V V X X X X X X X X X X X X X V V X V V V V L H X X X X X X X X X V V X V V V V L L X X X X X X X X X
A11, A9-0
CS
RAS
CAS
Row Address L X H X L Column H Address L A0~A8 H OP code X X X X X X X X X X X X X X X X X X
Any (Power Down) Any
L L L L L L L L L L H L L L H L H L H L L
L L L H H H H L L H X H L L X H X H X H H
H H H L L L L L L H X H L L X H X H X H H X X X
WE H L L L L H H L L H X L H H X H X H X H
L X X X
Deep Power Down Exit Any L HXX XX X H X Data Write Enable Active H X LX XX X X X Data Mask Disable Active H XHX XX X X X Note: 1. V = Valid data, X = Don't Care, L = Low level, H = High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BA0, BA1signals. 4. Read burst stop with BST command for all burst types. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode.
Etron Confidential
5
Rev. 1.0
Apr. 2009
EtronTech
Functional Description
EM68916DVAA
This 128Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM. Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. The 128Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high speed operation. EM68916D is applied to reduce leakage and refresh currents while achieving very high speed. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. Single read or write access for the 128Mb Mobile DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls. Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0-A11 select the row). The address bits (BA0, BA1 select the bank, A0-A8 select the column) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Note that the DLL (Delay Lock Loop) circuitry used on standard DDR devices is not included in the Mobile DDR SDRAM. It has been omitted to save power. Prior to normal operation, the Mobile DDR SDRAM must be initialized.
Power-Up and Initialization
Mobile DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. To properly initialize the Mobile DDR SDRAM, this sequence must be followed: 1. To prevent device latch-up, it is recommended that core power (VDD) and I/O power (VDDQ) be from the same power source and be brought up simultaneously. If separate power sources are used, VDD must lead VDDQ. 2. Once power supply voltages are stable and CKE has been driven High, it is safe to apply the clock. 3. Once the clock is stable, a 200s (minimum) delay is required by the Mobile DDR SDRAM prior to applying an executable command. During this time, NOP or Deselect commands must be issued on the command bus. 4. Issue a Precharge All command. 5. Issue NOP or Deselect commands for at least tRP time. 6. Issue an Auto Refresh command followed by NOP or Deselect commands for at least tRFC time. Issue a second Auto Refresh command followed by NOP or Deselect commands for at least tRFC time. As part of the individualization sequence, two Auto Refresh commands must be issued. Typically, both of these commands are issued at this stage as described above. Alternately, the second Auto Refresh command and NOP or Deselect sequence can be issued between steps 10 and 11. 7. Using the Mode Register Set command, load the standard Mode Register as desired. 8. Issue NOP or Deselect commands for at least tMRD time. 9. Using the Mode Register Set command, load the Extended Mode Register to the desired operating modes. Note that the sequence in which the standard and extended mode registers are programmed is not critical. 10. Issue NOP or Deselect commands for at least tMRD time. 11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command.
Etron Confidential
6
Rev. 1.0
Apr. 2009
EtronTech
Mode Register Set(MRS)
EM68916DVAA
The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS Latency, Burst Type, and Burst Length to make the Mobile DDR SDRAM useful for a variety of applications. The default value of the Mode Register is not defined; therefore the Mode Register must be written by the user. Values stored in the register will be retained until the register is reprogrammed, the device enters Deep Power Down mode, or power is removed from the device. The Mode Register is written by asserting Low on CS , RAS , CAS , WE , BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A11 and BA0, BA1 in the same cycle in which CS , RAS , CAS and WE are asserted Low is written into the Mode Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the Mode Register. The Mode Register is divided into various fields depending on functionality. The Burst Length uses A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0 should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific codes for various burst lengths, burst types and CAS latencies.
Table 4. Mode Register Bitmap
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0
0
0
0
0
CAS Latency
BT
Burst Length
Mode Register
A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved
A3 Burst Type 0 Sequential 1 Interleave
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved
CK CK Command
NOP PRE ALL NOP NOP MRS*1 NOP
Any
Command
NOP
NOP
tRP*2
tMRD= 2*tCK
*1: MRS can be issued only with all banks in the idle state. *2: A minimum delay of tRP is required before issuing an MRS command.
Don't Care
Figure 3. Mode Register Set Cycle
Etron Confidential
7
Rev. 1.0
Apr. 2009
EtronTech
Burst Mode Operation
EM68916DVAA
Burst Mode operation is used to provide a constant flow of data to memory locations (write cycle) or from memory locations (read cycle). There are two parameters that define how the Burst Mode operates. These parameters include Burst Type and Burst Length and are programmed by addresses A0~A3 during the Mode Register Set command. Burst Type is used to define the sequence in which the burst data will be delivered from or stored to the DDR SDRAM. Two types of burst sequences are supported, Sequential and Interleaved. See the table below. The Burst Length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. The Burst Length can be programmed to have a value of 2, 4, or 8.
Table 5.Burst Definition
Burst Length 2 Start Address A3 A2 A1 A0 X X X 0 X X X 1 X X 0 0 X X 0 1 X X 1 0 X X 1 1 X 0 0 0 X 0 0 1 X 0 1 0 X 0 1 1 X 1 0 0 X 1 0 1 X 1 1 0 X 1 1 1 Sequential 0,1 1,0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3,4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave 0,1 1,0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
4
8
Etron Confidential
8
Rev. 1.0
Apr. 2009
EtronTech
Extended Mode Register Set (EMRS )
EM68916DVAA
The Extended Mode Register is designed to support Partial Array Self Refresh and Driver Strength. The EMRS cycle is not mandatory, and the EMRS command needs to be issued only when either PASR or DS is used. The Extended Mode Register is written by asserting Low on CS , RAS , CAS , WE , and BA0 and High on BA1 (the device should have all banks idle with no bursts in progress prior to writing into the Extended Mode Register, and CKE should be High). Values stored in the register will be retained until the register is reprogrammed, the device enters Deep Power Down mode, or power is removed from the device. The state of address pins A0~A11 and BA0, BA1 in the same cycle in which CS , RAS , CAS and WE are asserted Low is written into the Extended Mode Register. Two clock cycles, tMRD, are required to complete the write operation in the Extended Mode Register. A0~A2 are used for Partial Array Self Refresh and A5~A6 are used for Driver Strength. An automatic Temperature Compensated Self Refresh function is included with a temperature sensor embedded into this device. A3~A4 are no longer used to control this function; any inputs applied to A3~A4 during EMRS are ignored. All the other address pins, A7~A11 and BA0, must be set to Low for proper EMRS operation. Refer to the tables below for specific codes. If the user does not write values to the Extended Mode Register, DS defaults to Full Strength; and PASR defaults to the Full Array.
Table 6. Extend Mode Register Bitmap
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
1
0
0
0
0
DS
0
0
PASR
Extended Mode Register
A6 0 0 1 1
A5 0 1 0 1
Drive Strength Full Strength 1/2 Strength 1/4 Strength 1/8 Strength
A2 A1 A0 Partial Array Self Refresh Coverage 000 Full Array (All Banks) 001 Half of Full Array (BA1=0) 0 1 0 Quarter of Full Array (BA1=BA0=0) 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved
TEMPERATURE COMPENSATED SELF REFRESH
In order to reduce power consumption, a Mobile DDR SDRAM includes the internal temperature sensor and other circuitry to control Self Refresh operation automatically according to two temperature ranges: max. 40C and max. 85C
Table 7. IDD6 Specifications and Conditions
Temperature Range Max. 40C Max. 85C Self Refresh Current (IDD6) Full Array 200 160 1/2 of Full Array 150 110 1/4 of Full Array 120 90 Unit A A
PARTIAL ARRAY SELF REFRESH
For further power savings during Self Refresh, the PASR feature allows the controller to select the amount of memory that will be refreshed during Self Refresh. The refresh options are all banks (banks 0, 1, 2 and 3); two banks (bank 0 and 1); and one bank (bank 0). Write and Read commands can still affect any bank during standard operations, but only the selected banks will be refreshed during Self Refresh. Data in unselected banks will be lost.
Etron Confidential
9
Rev. 1.0
Apr. 2009
EtronTech
Bank Activation / Row Address Command
EM68916DVAA
The Bank Activation / Row Address command, also called the Active command, is issued by holding CAS and WE High with CS and RAS Low at the rising edge of the clock (CK). The DDR SDRAM has four independent banks, so two Bank Select Addresses (BA0, BA1) are required. The Active command must be applied before any read or write operation is executed. The delay from the Active command to the first Read or Write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Active command can be applied to the same bank. The minimum time interval between interspersed Active commands (Bank 0 to Bank 3, for example) is the bank to bank delay time (tRRD min).
Burst Read Operation
Burst Read operation in a DDR SDRAM is initiated by asserting CS and RAS Low while holding RAS and WE High at the rising edge of the clock (CK) after tRCD from the Active command. The address inputs (A0~A8) determine the starting address for the Burst. The Mode Register sets the type of burst (Sequential or Interleaved) and the burst length (2, 4, or 8). The first output data is available after the CAS Latency from the Read command, and the consecutive data bits are presented on the falling and rising edges of Data Strobe (DQS) as supplied by the DDR SDRAM until the burst is completed.
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE Low while holding RAS High at the rising edge of the clock (CK). The address inputs determine the starting column address. There is no write latency relative to DQS required for the Burst Write cycle. The first data for a Burst Write cycle must be applied at the first rising edge of the data strobe enabled after tDQSS from the rising edge of the clock when the Write command was issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. After the burst has finished, any additional data supplied to the DQ pins will be ignored.
Burst Interruption Read Interrupted by Read
Burst Read can be interrupted before completion of the burst by a new Read command to any bank. When the previous burst is interrupted, data bits from the remaining addresses are overridden by data from the new addresses with the full burst length. The data from the previous Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. The Read to Read interval is a minimum of 1 clock.
Read Interrupted by Burst Stop & Write
To interrupt Burst Read with a write command, the Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQ (output drivers) in a high impedance state. To ensure the DQ are tri-stated one cycle before the beginning of the write operation, the Burst Stop command must be applied at least 2 clock cycles for CL = 2 and at least 3 clock cycles for CL = 3 before the Write command.
Read Interrupted by Precharge
Burst Read can be interrupted by a Precharge of the same bank. A minimum of 1 clock cycle is required for the read precharge interval. A Precharge command to output disable latency is equivalent to the CAS latency.
Etron Confidential
10
Rev. 1.0
Apr. 2009
EtronTech
Write Interrupted by Write
EM68916DVAA
A Burst Write can be interrupted by the new Write command before completion of the previous Burst Write, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new addresses and the new data will be written into the device until the programmed Burst Length is satisfied.
Write Interrupted by Read & DM
A Burst Write can be interrupted by a Read command to any bank. The DQ must be in the high impedance state at least one clock cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read command is to be asserted, any residual data from the Burst Write sequence must be masked by DM. The delay from the last data to the Read command (tWTR) is required to avoid data contention inside the DRAM. Data presented on the DQ pins before the Read command is initiated will actually be written to the memory. A Read command interrupting a write sequence can not be issued at the next clock edge following the Write command.
Write Interrupted by Precharge & DM
A Burst Write can be interrupted by a Precharge of the same bank before completion of the previous burst. A write recovery time (tWR) is required from the last data to the Precharge command. When the Precharge command is asserted, any residual data from the Burst Write cycle must be masked by DM.
Burst Stop Command
The Burst Stop command is initiated by having RAS and CAS High with CS and WE Low at the rising edge of the clock only. The Burst Stop command has the fewest restrictions, making it the easiest method to use when terminating a burst operation before it has been completed. When the Burst Stop command is issued during a Burst Read cycle, both the data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the Mode Register. The Burst Stop command, however, is not supported during a Burst Write operation.
DM Masking Function
The DDR SDRAM has a Data Mask function that can be used in conjunction with the data write cycle only, not the read cycle. When the Data Mask is activated (DM High) during a write operation, the write data is masked immediately (DM to Data Mask latency is zero). DM must be issued at the rising edge or the falling edge of Data Strobe instead of at a clock edge.
Auto Precharge Operation
Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank / row that is addressed with the READ or WRITE command is automatically performed upon completion of the read or write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharging time (tRP) is completed. When the Auto Precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during a read or write cycle after tRAS (min) is satisfied.
Precharge Command
The Precharge command is issued when CS , RAS , and WE are Low and CAS is High at the rising edge of the clock (CK). The Precharge command can be used to precharge any bank individually or all banks simultaneously. The Bank Select addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For a write cycle, tWR (min) must be satisfied from the start of the last Burst Write cycle until the Precharge command can be issued. After tRP from the precharge, an Active command to the same bank can be initiated.
Etron Confidential
11
Rev. 1.0
Apr. 2009
EtronTech
Auto Refresh
EM68916DVAA
An Auto Refresh command is issued by having CS , RAS , and CAS held Low with CKE and WE High at the rising edge of the clock (CK). All banks must be precharged and idle for a tRP (min) before the Auto Refresh command is applied. The refresh addressing is generated by the internal refresh address counter. This makes the address bits Don't Care during an Auto Refresh command. When the refresh cycle is complete, all banks will be in the idle state. A delay between the Auto Refresh command and the next Active command or subsequent Auto Refresh command must be greater than or equal to the tRFC (min).
Self Refresh
A Self Refresh command is defined by having CS , RAS , CAS and CKE Low with WE High at the rising edge of the clock (CK). Once the Self Refresh command has been initiated, CKE must be held Low to keep the device in Self Refresh mode. During the Self Refresh operation, all inputs except CKE are ignored. The clock is internally disabled during Self Refresh operation to reduce power consumption. To exit the Self Refresh mode, supply a stable clock input before returning CKE high, assert Deselect or a NOP command, and then assert CKE high.
Power Down Mode
The device enters Power Down mode when CKE is brought Low, and it exits when CKE returns High. Once the Power Down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce power consumption. All banks should be in an idle state prior to entering the Precharge Power Down mode and CKE should be set high at least tXP prior to an Active command. During Power Down mode, refresh operations cannot be performed; therefore the device must remain in Power Down mode for a shorter time than the refresh period (tREF) of the device.
DEEP POWER DOWN
Deep Power Down achieves maximum power reduction by eliminating the power of the whole memory array and surrounding circuitry. Data will not be retained in the memory storage array, the Mode Register, or the Extended Mode Register once the device enters Deep Power Down mode. This mode is entered by having all banks idle then CS and WE held Low with RAS and CAS held High at the rising edge of the clock, while CKE is Low. This mode is exited by asserting CKE High, applying only NOP commands for 200 microseconds, and then continuing with steps 4 through 11 of the Power Up and Initialization sequence..
Etron Confidential
12
Rev. 1.0
Apr. 2009
EtronTech
Table 8. Absolute Maximum Rating
Symbol VIN, VOUT VDD, VDDQ TA TSTG PD Parameter I/O Pins Voltage Power Supply Voltage Ambient Temperature Storage Temperature Power Dissipation
EM68916DVAA
Rating -6/75 -0.5~2.7 -0.5~2.7 -25~85 - 55~150 0.7
Unit V V C C W
IOUT Short Circuit Output Current 50 mA Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the devices. 2. All voltages are referenced to VSS. 3. Functional operation should be restricted to Recommended Operating Conditions. 4. Exposure to higher than the recommended voltages for extended periods of time could affect device reliability
Table 9. Recommended D.C. Operating Conditions (VDD=1.7V~1.95V, TA =-25~85C)
Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input High Voltage (DC) Input Low Voltage (DC) Input leakage current Output leakage current Output High Voltage Symbol VDD VDDQ VIH (DC) VIL (DC) IIL IOZ VOH Min. 1.7 1.7 0.7 x VDDQ -0.3 -2 -5 0.9 x VDDQ Max. 1.95 1.95 VDDQ + 0.3 0.3 x VDDQ 2 5 Unit V V V V A A V IOH=-0.1mA Note
Output Low Voltage VOL 0.1 x VDDQ V IOL=0.1mA Note: These parameters are guaranteed by design, periodically sampled and are not 100% tested.
Table 10. Capacitance (VDD=1.7V~1.95V, f = 1MHz, TA = 25 C)
Symbol CIN1 Parameter Input Capacitance (CK, CK ) Min. 1.5 Max. 3 Delta 0.25 Unit pF pF pF
CIN2 Input Capacitance (all other input-only pins ) 1.5 3 0.5 CI/O DQ, DQS, DM Input/Output Capacitance 3 5 0.5 Note: These parameters are guaranteed by design, periodically sampled and are not 100% tested.
Etron Confidential
13
Rev. 1.0
Apr. 2009
EtronTech
Table 11. DC Characteristics (VDD=1.7V~1.95V, TA =-25~85C)
Parameter & Test Condition Operating one bank active-precharge current: tRC=tRC(min); tCK=tCK(min); CKE is HIGH; CS is HIGH between valid commands; Address inputs are SWITCHING; data bus inputs are STABLE Precharge power-down standby current: All banks idle, CKE is LOW; CS is HIGH, tCK=tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE Precharge power-down standby current with clock stop: All banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Precharge non power-down standby current: All banks idle, CKE is HIGH; CS is HIGH, tCK=tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE Precharge non power-down standby current with clock stop: All banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Active power-down standby current: One bank active, CKE is LOW; CS is HIGH, tCK=tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE Active power-down standby current with clock stop: One bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Active non power-down standby current: One bank active, CKE is HIGH; CS is HIGH, tCK=tCK(min) address and control inputs are SWITCHING; data bus inputs are STABLE Active non power-down standby current with clock stop: One bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Operating burst read current: One bank active; BL = 4; CL = 3; tCK=tCK(min); continuous read bursts; IOUT = 0 mA address inputs are SWITCHING; 50% data change each burst transfer Operating burst write current: One bank active; BL = 4; tCK=tCK(min); continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer Auto-Refresh current: tRFC = tRFC(min); tCK=tCK(min); burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Self refresh current: TCSR Range CKE is LOW, CK = LOW, CK = HIGH; Extended Mode Full Array Register set to all address and control inputs are STABLE; 1/2 Full Array data bus inputs are STABLE 1/4 Full Array Deep Power Down Mode Current
EM68916DVAA
Symbol -6 MAX 45 40 -75 Unit
IDD0
mA
IDD2P
0.1
0.1
mA
IDD2PS
0.1
0.1
mA
IDD2N
15
15
mA
IDD2NS
8
8
mA
IDD3P
3
3
mA
IDD3PS
2
2
mA
IDD3N
20
20
mA
IDD3NS
10
10
mA
IDD4R
120
95
mA
IDD4W
120
95
mA
IDD5
70 Max. 40
70 Max.85 200 150 120 10
mA
IDD6
160 110 90
A A A A
IDD8
Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time per two clock cycles.
Etron Confidential
14
Rev. 1.0
Apr. 2009
EtronTech
Symbol tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQH tRC tRFC tRAS tRCD tRP tRRD twR tDAL tWTR tCCD tMRD tXSR tXP tREFI Note:
Clock cycle time Clock high level width Clock low level width DQS-out access time from CK, CK Output access time from CK, CK DQS-DQ Skew Read preamble Read postamble CK to valid DQS-in DQS-in setup time DQS write preamble DQS write postamble DQS in high level pulse width DQS in low level pulse width Address and Control input setup time Address and Control input hold time DQ & DM setup time to DQS DQ & DM hold time to DQS Clock half period Output DQS valid window Row cycle time Refresh row cycle time Row active time
EM68916DVAA
-6 Min.
CL = 2 CL = 3 12 6 0.45 0.45 2 2 0.9 0.4 0.75 0 0.25 0.4 0.4 0.4 1.1 1.1 0.6 0.6
Table 12. Electrical AC Characteristics (VDD=1.7V~1.95V, TA =-25~85C)
Parameter -75 Max.
100 0.55 0.55 5.5 5.5 0.5 1.1 0.6 1.25 0.6 0.6 0.6 100K 15.6
Min.
12 7.5 0.45 0.45 2 2 0.9 0.4 0.75 0 0.25 0.4 0.4 0.4 1.3 1.3 0.8 0.8
Max.
100 0.55 0.55 6 6 0.6 1.1 0.6 1.25 0.6 0.6 0.6 100K 15.6
Unit Note ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK tCK tCK ns ns s
2 1 1
3
1 1 4, 5 4, 5
tCLMIN or tCHMIN tHP - 0.65
60 110 42 18 18 12 12 tWR+tRP 2 1 2 200 25 -
tCLMIN or tCHMIN tHP - 0.75
67.5 110 45 22.5 22.5 15 15 tWR+tRP 1 1 2 200 25 -
RAS to CAS Delay for Read or Write
Row precharge time Row active to Row active delay Write recovery time Auto precharge write recovery + Precharge Internal Write to Read Delay Col. Address to Col. Address delay Mode register set cycle time Self refresh exit to next valid command delay Exit Power Down mode to first valid command Refresh interval time
8
7
6
1. Table 13.Input Setup / Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 1.0 0.8 0.6 tIS (ps) 0 +50 +100 tIH (ps) 0 +50 +100
This derating table is used to increase tIS / tIH in the case where the input slew rate is below 1.0V/ns.
Etron Confidential
15
Rev. 1.0
Apr. 2009
EtronTech
EM68916DVAA
2. Driver Strength should be selected based on actual system loading conditions. Figure 3, the AC Output Load Circuit, represents the reference load used in defining the relevant timing parameters of this device.The 20pF load capacitance is not expected to be a precise representation of either a typical system load or the production test environment but is appropriate for Full Driver Strength. Setting the output drivers to 1/2 Driver Strength, for a further example, is appropriate for a 10pF load. 3. The specific requirement is that DQS be Valid (High or Low) on or before this CK edge. The case shown (DQS going from High-Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 4. Table 14. I/O Setup / Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 1.0 0.8 0.6 5. Table 15. I/O Delta Rise / Fall Derating I/O Delta Rise / Fall Rate (ns/V) 1.0 0.25 tDS (ps) 0 +50 tDH (ps) 0 +50 tDS (ps) 0 +75 +150 tDH (ps) 0 +75 +150
This derating table is used to increase tDS / tDH in the case where the I/O slew rate is below 1.0V/ns
0.50 +100 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise / Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For example, if SlewRate1 = 1.0V/ns and SlewRate2 = 0.8V/ns, then the Delta Rise / Fall Rate = -0.25ns/V. 6. There must be at least one clock (CK) pulse during the tXP period. 7. tWTR is referenced from the positive clock edge after the last Data In pair. 8. tWR is referenced from the positive clock edge after the last desired Data In pair.
Etron Confidential
16
Rev. 1.0
Apr. 2009
EtronTech
Parameter Input High Voltage (AC) Input Low Voltage (AC) Symbol VIH (AC) VIL (AC) Min. 0.8 x VDDQ -0.3 0.4 x VDDQ
EM68916DVAA
Max. VDDQ+0.3 0.2 x VDDQ 0.6 x VDDQ Unit Note V V V 1 1 2
Table 16. Recommended A.C. Operating Conditions (VDD=1.7V~1.95V, TA =-25~85C)
Input Crossing Point Voltage, CK and CK inputs VIX (AC) Note:
1. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2. The value of VIX is expected to equal 0.5 x VDDQ of the transmitting device and must track variation in the DC level of the same.
Table 17. LVCMOS Interface
Reference Level of Output Signals Output Load Input Signal Levels (VIH/ VIL) Input Signals Slew Rate Reference Level of Input Signals 0.5 x VDDQ Reference to the Test Load 0.8 x VDDQ / 0.2 x VDDQ 1 V/ns 0.5 x VDDQ
Figure 4. LVCMOS A.C. Test Load 0.5 x VDDQ
50 Output Z0=50 20pF
Etron Confidential
17
Rev. 1.0
Apr. 2009
EtronTech
Timing Waveforms Figure 5. Initialization Waveform Sequence
VDD VDDQ CK CK CKE Command Address A10 BA0,1 DM DQ,DQS
(High-Z) All Banks NOP PRE ARF ARF 200 S
EM68916DVAA
tCK
tRP
tRFC
tRFC
tMRD
tMRD
MRS
MRS
ACT
CODE
CODE
RA
CODE
BA0=L BA1=L
CODE
BA0=L BA1=H
RA
BA
VDD / VDDQ powered up Clock stable
Load Mode Reg.
Load Ext. Mode Reg.
Don't Care
Figure 6. Basic Timing Parameters for Commands
tCK CK CK
tIS tIH
tCH
tCL
Input
Valid
Valid
Valid
Don't Care
Notes: Input = A0 - A11, BA0,BA1, CKE, CS, RAS, CAS, WE;
Etron Confidential
18
Rev. 1.0
Apr. 2009
EtronTech
Figure 7. NOP Command
CK CK CKE CS RAS CAS WE A0-A11 BA0,1
(High)
EM68916DVAA
Don't Care
Etron Confidential
19
Rev. 1.0
Apr. 2009
EtronTech
Figure 8. Mode Register Set Command
CK CK CKE CS RAS CAS WE A0-A11 BA0,1
Code (High)
EM68916DVAA
Code
Don't Care
Figure 9. Mode Register Set Command Timing
CK CK Command
MRS NOP Valid
tMRD Address
Code Valid
Don't Care
Notes: Code = Mode Register / Extended Mode Register selection (BA0, BA1) and op-code (A0- A11)
.
Etron Confidential
20
Rev. 1.0
Apr. 2009
EtronTech
Figure 10. Active Command
CK CK CKE CS RAS CAS WE A0-A11 BA0,1 RA BA
(High)
EM68916DVAA
Don't Care
BA = Bank Address RA = Row Address
Figure 11. Bank Activation Command Cycle
CK CK Command A0-A11 BA0,1
ACT NOP ACT NOP NOP
RD/WR
NOP
Row
Row
Col
BA x
BA y
BA y
tRRD
tRCD
Don't Care
Etron Confidential
21
Rev. 1.0
Apr. 2009
EtronTech
Figure 12. Read Command
CK CK CKE CS RAS CAS WE A0-A8 A10 BA
CA Enable AP AP Disable AP BA (High)
EM68916DVAA
Don't Care
BA = Bank Address CA = Column Address AP = Auto Precharge
Etron Confidential
22
Rev. 1.0
Apr. 2009
EtronTech
Figure 13. Basic Read Timing Parameters
tCK CK CK tCK tCH tCL
EM68916DVAA
tAC max
DQS
tDQSCK tRPRE tDQSQ max tAC
tDQSCK tRPST tHZ
DO n DO n+1 DO n+2 DO n+3
DQ
tLZ tDQSCK
tQH tDQSCK tRPST tDQSQ max
tQH
tAC min
DQS
tRPRE
tAC DQ
DO n DO n+1 DO n+2
tHZ
DO n+3
tLZ
tQH
tQH
(1) DO n = Data Out from column n (2) All DQ are valid tAC after the CK edge. All DQ are valid tDQSQ after the DQS edge, regardless of tAC
Don't Care
Etron Confidential
23
Rev. 1.0
Apr. 2009
EtronTech
Figure 14. Read Burst Showing CAS Latency
CK CK Command Address
READ NOP NOP NOP
EM68916DVAA
NOP
NOP
BA, Col n
CL = 2 DQS DQ CL = 3 DQS DQ
DO n
DO n
Don't Care
(1) DO n = Data Out from column n (2) BA, Col n = Bank A, Column n (3) Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n (4) Shown with nominal tAC, tDQSCK and tDQSQ
Figure 15. Consecutive Read Bursts
CK CK Command Address
READ NOP READ NOP NOP NOP
BA, Col n
BA, Col b
CL = 2 DQS DQ CL = 3 DQS DQ
DO n
DO b
DO n
DO b
Don't Care
(1) DO n (or b) = Data Out from column n (or column b) (2) Burst Length = 4 or 8 (if 4, the bursts are concatenated; if 8 , the second burst interrupts the first) (3) Read bursts are to an active row in any bank (4) Shown with nominal tAC, tDQSCK and tDQSQ
Etron Confidential
24
Rev. 1.0
Apr. 2009
EtronTech
Figure 16. Non-Consecutive Read Bursts
CK CK Command Address
READ NOP NOP READ
EM68916DVAA
NOP
NOP
BA, Col n
BA, Col b
CL = 2 DQS DQ CL = 3 DQS DQ
DO n
DO b
DO n
Don't Care
(1) DO n (or b) = Data Out from column n (or column b) (2) BA Col n (b) = Bank A, Column n (b) (3) Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n (b) (4) Shown with nominal tAC, tDQSCK and tDQSQ
Figure 17. Random Read Bursts
CK CK Command Address
READ READ READ READ NOP NOP
BA, Col n
BA, Col x
BA, Col b
BA, Col g
CL = 2 DQS DQ CL = 3 DQS DQ
DO n
DO n'
DO x
DO x'
DO b
DO b'
DO g
DO g'
DO n
DO n'
DO x
DO x'
DO b
DO b'
Don't Care
(1) DO n, etc. = Data Out from column n, etc. n', x', etc. = Data Out elements, according to the programmed burst order (2) BA, Col n = Bank A, Column n (3) Burst Length = 2, 4 or 8 in cases shown (if burst of 4 or 8 , the burst is interrupted) (4) Reads are to active rows in any banks
Etron Confidential
25
Rev. 1.0
Apr. 2009
EtronTech
Figure 18. Terminating a Read Burst
CK CK Command Address
READ BST NOP NOP
EM68916DVAA
NOP
NOP
BA, Col n
CL = 2 DQS DQ CL = 3 DQS DQ
Don't Care
(1) DO n = Data Out from column n (2) BA Col n = Bank A, Column n (3) Cases shown are bursts of 4 or 8 teminated after 2 data elements. (4) Shown with nominal tAC, tDQSCK and tDQSQ
Etron Confidential
26
Rev. 1.0
Apr. 2009
EtronTech
Figure 19. Read to Write
CK CK Command Address
READ BST NOP WRITE
EM68916DVAA
NOP
NOP
BA, Col n
BA, Col b
CL = 2 DQS DQ DM
tDQSS
DO n
Command Address
READ
BST
NOP
NOP
WRITE
NOP
BA, Col n
BA, Col b
CL = 3 DQS DQ DM
DO n
Don't Care
(1) DO n = Data Out from column n; DI b = Data In to column b (2) Burst length = 4 or 8 in the cases shown; if the burst length is 2, the BST command can be ommitted (3) Shown with nominal tAC, tDQSCK and tDQSQ
Etron Confidential
27
Rev. 1.0
Apr. 2009
EtronTech
Figure 20. Read to precharge
CK CK Command Address
READ NOP PRE Bank (a or all) NOP
EM68916DVAA
NOP
ACT
BA, Col n
BA, Row
CL = 2 DQS DQ CL = 3 DQS DQ
tRP
DO n
DO n
(1) DO n = Data Out from column n (2) Cases shown are either uninterrupted burst of 4, or interrupted bursts of 8. (3) Shown with nominal tAC, tDQSCK and tDQSQ. (4) Precharge may be applied at (BL/2) tCK after the READ command. (5) Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks. (6) The ACTIVE command may be applied if tRC has been met.
Don't Care
Figure 21. Burst Terminate Command
CK CK CKE CS RAS CAS WE A0-A11 BA0,BA1
(High)
Don't Care
Etron Confidential
28
Rev. 1.0
Apr. 2009
EtronTech
Figure 22. Write Command
CK CK CKE CS RAS CAS WE A0-A8 A10 BA0,1
CA Enable AP AP Disable AP BA (High)
EM68916DVAA
Don't Care
BA = Bank Address CA = Column Address AP = Auto Precharge
Etron Confidential
29
Rev. 1.0
Apr. 2009
EtronTech
Figure 23. Basic Write Timing Parameters
tCK CK CK tDSH
Case 1: tDQSS = min
EM68916DVAA
tCH tCL
tDQSS
tDQSH
tDSH tWPST tDQSL
DQS tWPRES tWPRE tDS DQ, DM
DI n
tDH
Case 2: tDQSS = max
tDQSS
tDQSH
tDSS
tDSS tWPST
DQS tWPRES tWPRE tDS DQ, DM
DI n
tDH
tDQSL
Don't Care
(1) DI n = Data In for column n (2) 3 subsequent elements of Data In are applied in the programmed order following DI n. (3) tDQSS: each rising edge of DQS must fall within the 25% window of the corresponding positive clock edge.
Etron Confidential
30
Rev. 1.0
Apr. 2009
EtronTech
Figure 24. Write Burst (min. and max. tDQSS)
CK CK Command Address
WRITE NOP NOP NOP
EM68916DVAA
NOP
NOP
BA, Col b
tDQSS min DQS DQ DM
tDQSS max DQS DQ DM
Don't Care
(1) DI b = Data In to column b. (2) 3 subsequent elements of Data In are applied in the programmed order following DI b. (3) A non-interrupted burst of 4 is shown. (4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
Etron Confidential
31
Rev. 1.0
Apr. 2009
EtronTech
Figure 25. Concatenated Write Bursts
CK CK Command Address
WRITE NOP WRITE NOP
EM68916DVAA
NOP
NOP
BA, Col b
BA, Col n
tDQSS min DQS DQ DM
DI b
DI n
tDQSS max DQS DQ DM
DI b
DI n
Don't Care
(1) DI b (n) = Data In to column b (column n). (2) 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements of Data In are applied in the programmed order following DI n. (3) Non-interrupted bursts of 4 are shown. (4) Each WRITE command may be to any active bank
Etron Confidential
32
Rev. 1.0
Apr. 2009
EtronTech
Figure 26. Non-Concatenated Write Bursts
CK CK Command Address
WRITE NOP NOP WRITE
EM68916DVAA
NOP
NOP
BA, Col b
BA, Col n
tDQSS max DQS DQ DM
Don't Care
(1) DI b (n) = Data In to column b (or column n). (2) 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements of Data In are applied in the programmed order following DI n. (3) Non-interrupted bursts of 4 are shown. (4) Each WRITE command may be to any active bank and may be to the same or different devices
Etron Confidential
33
Rev. 1.0
Apr. 2009
EtronTech
Figure 27. Random Write Cycles
CK CK Command Address
WRITE WRITE WRITE WRITE
EM68916DVAA
WRITE
BA, Col b
BA, Col x
BA, Col n
BA, Col a
BA, Col g
tDQSS max DQS DQ DM
DI b
DI b
DI x
DI x
DI n
DI n
DI a
DI a
Don't Care
(1) DI b etc. = Data In to column b, etc. ; b', etc. = the next Data In following DI b, etc. according to the programmed burst order (2) Programmed burst length = 2, 4, or 8 in cases shown. If burst of 4 or 8 , burst would be truncated. (3) Each WRITE command may be to any active bank and may be to the same or different devices.
Figure 28. Non-Interrupting Write to Read
CK CK Command Address
WRITE NOP NOP NOP NOP READ NOP
BA, Col b
BA, Col n
tDQSS max DQS DQ DM
tWTR
DI b
(1) DI b = Data In to column b. 3 subsequent elements of Data In are applied in the programmed order following DI b. (2) A non-interrupted burst of 4 is shown. (3) tWTR is referenced from the positive clock edge after the last Data In pair. (4) A10 is LOW with the WRITE command (Auto Precharge is disabled) (5) The READ and WRITE commands are to the same device but not necessarily to the same bank.
Don't Care
Etron Confidential
34
Rev. 1.0
Apr. 2009
EtronTech
Figure 29. Interrupting Write to Read
CK CK Command Address
WRITE NOP NOP NOP READ
EM68916DVAA
NOP
NOP
BA, Col b
BA, Col n
tDQSS max DQS DQ DM
tWTR
CL = 3
DI b
(1) DI b = Data In to column b. DO n = Data Out from column n. (2) An interrupted burst of 4 is shown, 2 data elements are written. 3 subsequent elements of Data In are applied in the programmed order following DI b. (3) tWTR is referenced from the positive clock edge after the last Data In pair. (4) A10 is LOW with the WRITE command (Auto Precharge is disabled) (5) The READ and WRITE commands are to the same device but not necessarily to the same bank.
Don't Care
Figure 30. Non Interrupting Write to Precharge
CK CK Command Address
WRITE NOP NOP NOP NOP PRE BA a (or all)
BA, Col b
tDQSS max DQS DQ DM
tWR
DI b
Don't Care
(1) DI b = Data In to column b. 3 subsequent elements of Data In are applied in the programmed order following DI b. (2) A non-interrupted burst of 4 is shown. (3) tWR is referenced from the positive clock edge after the last Data in pair. (4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
Etron Confidential
35
Rev. 1.0
Apr. 2009
EtronTech
Figure 31. Interrupting Write to Precharge
CK CK Command Address
WRITE NOP NOP NOP
EM68916DVAA
PRE BA a (or all)
NOP
BA, Col b
tDQSS max DQS DQ DM
tWR *2
DI b
*1
*1
*1
*1
(1) DI b = Data In to column b. (2) An interrupted burst of 4 or 8 is shown, 2 data elements are written. (3) tWR is referenced from the positive clock edge after the last desired Data in pair. (4) A10 is LOW with the WRITE command (Auto Precharge is disabled) (5) *1 = can be Don't Care for programmed burst length of 4 (6) *2 = for programmed burst length of 4, DQS becomes Don't Care at this point
Don't Care
Figure 32. Precharge Command
CK CK CKE CS RAS CAS WE A0-A9 A11
All Banks (High)
A10
One Bank
BA0,1
BA
Don't Care
BA = Bank Address (if A10 = L, otherwise Don't Care)
Etron Confidential
36
Rev. 1.0
Apr. 2009
EtronTech
Figure 33. Auto Refresh Command
CK CK CKE CS RAS CAS WE A0-A11 BA0,1
(High)
EM68916DVAA
Don't Care Figure 34. Self Refresh Command
CK CK CKE CS RAS CAS WE A0-A11 BA0,1
Don't Care
Etron Confidential
37
Rev. 1.0
Apr. 2009
EtronTech
Figure 35. Auto Refresh Cycles Back-to-Back
CK CK Command
PRE
EM68916DVAA
tRP
NOP ARF NOP
tRFC
NOP ARF NOP
tRFC
NOP ACT
Address
Ba A, Row n
A10 (AP) DQ
Pre All
Row n High-Z
Ba A, Row n = Bank A, Row n
Don't Care
Figure 36. Self Refresh Entry and Exit
CK CK CKE Command
PRE NOP ARF NOP NOP NOP ARF NOP ACT
tRP
tRFC
tXSR
tRFC
Address
Ba A, Row n
A10 (AP) DQ
Pre All
Row n High-Z
Enter Self Refresh Mode
Exit From Self Refresh Mode
Any Command (Auto Refresh Recommended)
Don't Care
Etron Confidential
38
Rev. 1.0
Apr. 2009
EtronTech
Figure 37. Power-Down Entry and Exit
CK CK CKE Command
PRE NOP NOP NOP
EM68916DVAA
tRP
tCKE
tXP
NOP
NOP
Valid
Address
Valid
A10 (AP) DQ
Pre All
Valid High-Z
Power Down Entry
Exit From Power Down
Any Command
Precharge Power-Down mode shown: all banks are idle and tRP is met when Power-Down Entry command is issued
Don't Care
Figure 38. Deep Power-Down Entry and Exit
T0 CK CK CKE T1 Ta0 Ta1 Ta2
Command Address DQS DQ DM
NOP
DPD
NOP
Valid
Valid
tRP
Enter DPD Mode
T = 200s Exit DPD Mode
Don't Care
(1) Clock must be stable before exiting Deep Power-Down mode. That is, the clock must be cycling within specifications by Ta0 (2) Device must be in the all banks idle state prior to entering Deep Power-Down mode (3) 200s is required before any command can be applied upon exiting Deep Power-Down mode (4) Upon exiting Deep Power-Down mode a PRECHARGE ALL command must be issued, followed by two AUTO REFRESH commands and a load mode register sequence
Etron Confidential
39
Rev. 1.0
Apr. 2009
EtronTech
Figure 39. VFBGA 60ball 8x10x1.0mm(max) package outline
EM68916DVAA
Pin 1
Top View
Bottom View
Side View
Detail "A"
Symbol A A1 A2 D E D1 E1 e b F
Dimension in inch Min Nom Max --0.039 0.012 0.014 0.016 0.022 0.023 0.024 0.311 0.315 0.319 0.390 0.394 0.398 -0.252 --0.283 --0.031 -0.016 0.018 0.020 -0.126 --
Dimension in mm Min Nom Max --1.0 0.30 0.35 0.40 0.54 0.58 0.62 7.9 8.0 8.1 9.9 10 10.1 -6.4 --7.2 --0.8 -0.4 0.45 0.5 -3.2 --
Etron Confidential
40
Rev. 1.0
Apr. 2009

▲Up To Search▲

Price & Availability of EM68916DVAA-6H

	To Download EM68916DVAA-6H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .